Steven A. Przybylski

Author

Stanford University

Also Known As

S. Przybylski, S.A. Przybylski, STEVEN A. PRZYBYLSKI, Steven A. Przybylski, Steven Przybylski

Publications

981

Citations

H-Index

Concepts

All Affiliations

Stanford University

About

Steven A. Przybylski is an author at Stanford University specializing in computer engineering, computer architecture, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	15	733
2	Computer Engineering	14	15	733
3	Computer Science	13	14	692
4	Electrical Engineering	2	2	33
5	Management	1	1	21

Steven A. Przybylski

Publications

733

Citations

H-Index

Page 1

	Year	Citations
An analytical access time model for on-chip cache memories T. Wada, S.C.S. Rajan, Steven A. Przybylski IEEE Journal of Solid-State Circuits Non-volatile MemoryEngineeringMemory DesignOn-chip Cache MemoriesComputer Architecture	1992	144
MIPS John L. Hennessy, Norman P. Jouppi, Steven A. Przybylski, ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter System On ChipHardware ArchitectureEngineeringFast Pipelined EngineComputer Engineering	1982	94
The performance impact of block sizes and fetch strategies Steven A. Przybylski ACM SIGARCH Computer Architecture News Performance BenchmarkingEngineeringComputer ArchitectureBlock SizePerformance Issue	1990	81
Performance tradeoffs in cache design Steven A. Przybylski, Mark Horowitz, John L. Hennessy EngineeringMemory DesignComputer ArchitectureSystem-level DesignPower Optimization	2003	59
Characteristics of performance-optimal multi-level cache hierarchies Steven A. Przybylski, Mark Horowitz, John L. Hennessy ACM SIGARCH Computer Architecture News Cluster ComputingEngineeringComputer ArchitectureProcessor ArchitectureHardware Security	1989	57
MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache Mark Horowitz, Paul Chow, D. Stark, IEEE Journal of Solid-State Circuits Hardware SecuritySystem On Chip20-Mips PeakEngineeringVlsi Design	1987	51
Organization and VLSI implementation of MIPS Steven A. Przybylski, Thomas R. Gross, John L. Hennessy, EngineeringVlsi DesignComputer ArchitectureNmos Vlsi ChipVlsi Implementation	1984	45
Characteristics of performance-optimal multi-level cache hierarchies Steven A. Przybylski, Mark Horowitz, John L. Hennessy Cluster ComputingEngineeringComputer ArchitectureProcessor ArchitectureHardware Security	1989	44
A CMOS RISC Processor with Integrated System Functions. John P. Moussouris, Lester M. Crudele, Danny Freitas, COMPCON System On ChipEngineeringRisc-vCmos Risc ProcessorComputer Engineering	1986	41
Measurement and evaluation of the MIPS architecture and processor Thomas R. Gross, John L. Hennessy, Steven A. Przybylski, ACM Transactions on Computer Systems EngineeringComputer ArchitectureSoftware EngineeringNmos Vlsi ChipProcessor Architecture	1988	25

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