Modeling of imprint in hysteresis loop of ferroelectric thin films with top and bottom interface layers

Abstract

The imprint of a ferroelectric thin film capacitor is studied using an improved model consisting of two nonswitching thin interface layers near the top and bottom electrodes. The difference in electrical conductivity between the two interface layers induces voltage offset and deformation behaviors in hysteresis loops. Size dependence of shift effect of Bi4−xNdxTi3O12 thin film is explained qualitatively by taking into account the thickness ratio of the interface layer and the bulk film. Various shifts and anamorphic shapes with different electrodes and processes have been effectively reproduced through changing the layer conductivities. The simulated shifted hysteresis loops agree well with the experiment. Theoretical prediction based on this approach may provide a method to reduce imprint failure.