2001 · 14 citations · 5 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsField-programmable Gate ArraysConfigurable Logic BlocksDigital Image ProcessingImage CompressionImage QuantizationReconfigurable Embedded SystemsReconfigurable System ArchitectureCamera SystemsCell Library DesignConfigurable Logic Cell DesignImage Processing AcceleratorsPipelined Digital CircuitsReconfigurable Embedded ProcessorsReconfigurable Image Processing SystemsRun-time Reconfigurable Architecture
Abstract- A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time re-configurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-pm single-poly, triple-metal process. It can run up to 40 MHz at 3.3V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc. I.
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P.A. Ruetz, Po Tong, D.A. Luthi et al. · The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology · 1993 · 20 citations