IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1994 · 152 citations · 14 references
EngineeringVlsi DesignHardware AlgorithmComputer ArchitectureHardware SystemsHardware SecurityFpga Technology MappingComputing SystemsComputational GeometryDepth Trade-offComputer EngineeringComputer ScienceReconfigurable ArchitectureMicroelectronicsFpga DesignArea/depth Trade-offLogic SynthesisHardware AccelerationVlsi ArchitectureDepth Relaxation Operations
In this paper, we study the area and depth trade-off in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have developed a polynomial time optimal algorithm for computing an area-minimum mapping solution without node duplication for a K-bounded general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by most existing mapping algorithms in terms of both area and depth minimization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Improved logic synthesis algorithms for table look up architectures
Rajeev Murgai, Narendra Shenoy, Robert K. Brayton et al. · 2002 · 208 citations
Logic synthesis for programmable gate arrays
Rajeev Murgai, Yoshihito Nishizaki, Narendra Shenoy et al. · 1990 · 192 citations