A four-level VLSI bipolar metallization design with chemical-mechanical planarization

Abstract

A high-performance four-level semiconductor device wiring fabrication process has been developed for bipolar devices in Enterprise System/9000™ (ES/9000™) processors. The reliable interconnection of large numbers of devices on a single integrated circuit chip has been enhanced by planarizing insulators and metals using chemical-mechanical polishing processes, by a novel contact stud structure, and by a Ti-clad Al-Cu metallurgy. This paper describes the structure of the four-level wiring and elements of the process, including the silicon contacts, techniques for depositing metal and oxide to cover features with high aspect ratios, high-temperature fine-line lift-off stencils, and high-density, area array solder terminals.