Automatic impedance control

Abstract

The authors describe circuits and techniques that provide automatic on-chip impedance matching between a series-terminated, low-voltage swing, CMOS I/O pad, and an external interconnect. The automatic impedance control technique employs a digitally controlled output impedance driver, a high-gain, low-voltage differential receiver, and an IEEE-1149.1-1990 compatible test access port. The techniques presented here design circuits that compensate for external environmental variations. A component to test these circuits uses a 0.8- mu m effective gate-length process. The test components exhibit 2-ns I/O latencies with 1-ns rise/fall times and match impedances between 30 and 100 Omega .< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>