Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation

Abstract

Planar bulk CMOS in subthreshold operation allows an important reduction of the power consumption. This can lead the way to new ultra low-power applications with autonomous devices supplied by energy harvesting techniques. However, subthreshold circuits are more sensitive to threshold voltage variations and require new layout optimizations. We propose a methodology to design robust standard cell circuits to cope with the challenges of reducing the supply voltage. We provide evaluations in the 180 nm technology node for area, power, timing and sensitivity to variations for a frequency division chain circuit — commonly used in watches — and for an ultra low-power 32-bit processor. The circuits developed with our subthreshold standard cell library are supplied at 0.4 V and can also work at 1.0 V, allowing multiple modes of operation for power management. We compare them to the same designs using a mature low-power library supplied at 1.0 V.