2008 · 15 citations · 0 references
EngineeringManufacturing EngineeringMaterials ScienceElectronic MaterialsManufacturing ProcessesSemiconductor DevicesChip PackagingIntegrated Circuit FabricationInterconnect TechnologyPackaging EngineeringVery-large-scale Integration LayoutWafer Bonding3D Integrated CircuitsAdvanced PackagingDie-to-wafer BondingManufacturingPower ConsumptionSignal TransmissionThree-dimensional IntegrationWafer-level Packaging
There is no question that 3D integration will be the next generation of packaging. This requires new technologies from ultra thin wafer handling to wafer to wafer bonding with 3D inter substrate connections. TSV is a process in which wafers are thinned, stacked and interconnected to significantly improve electrical performance such as signal transmission, interconnect density, reduced power consumption, form factor and manufacturing costs.