IEEE Transactions on Electron Devices · 1997 · 26 citations · 9 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSemiconductor DevicesHigh-frequency Semiconductor DevicesIntegrated Circuit DesignRadio-frequency Integrated CircuitsTransistor BiasingBase ResistanceHigh-speed Circuit Design
Expressions relating the bandwidth of a common-emitter (CE) amplifier stage and the small-signal CML gate delay time to directly measurable transistor parameters, such as f/sub T/, f/sub max/, and input bandwidth f/sub /spl upsi//, are presented. They are valid for an arbitrary division of the base resistance and base-collector depletion capacitance into internal and external components. No resistance measurements are needed. It is shown that the transistor input bandwidth f/sub /spl upsi// is an important figure of merit for the speed of a CE stage. Under a given bias condition, f/sub /spl upsi// is determined by the base resistance and the cut-off frequency. In most cases the value of the maximum oscillation frequency f/sub max/ is only of minor importance. It would therefore be more meaningful to present besides f/sub T/ also f/sub /spl upsi// instead of f/sub max/ as a figure of merit for transistors for high-speed, low-power analog and digital circuits.
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Analysis and Design of Analog Integrated Circuits
W.R. Betts · Electronics and Power · 1978 · 3.8K citations