2014 · 17 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsInstrumentationSystem-on-chip DesignAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignAnalog Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Integrated CircuitsComparator DesignMetastabilityMetastability Mitigation
A 12-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented. A sample-and-hold amplifier (SHA) is employed to convert single-ended input signal into fully-differential signal. The proposed SAR ADC exploits V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CM</sub> -based switching method with a hybrid RC digital-to-analog converter (DAC) to reduce the size of the capacitive DAC. A three-stage preamplifier followed by a latch is employed for a comparator to avoid the metastability problem and achieve high accuracy comparison. The prototype ADC fabricated in a 0.18 μm CMOS process shows the measured DNL and INL within 0.48 LSB and 0.76 LSB, respectively. The ADC shows the maximum SNDR and SFDR of 64.2 dB and 80.4 dB with a 2.8 V supply while consuming 1.16 mW. It occupies an active die area of 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
6
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
Yan Zhu, Chi‐Hang Chan, U-Fat Chio et al. · IEEE Journal of Solid-State Circuits · 2010 · 713 citations
Engineering, Computer Engineering, Electrical Engineering +17
Ji‐Yong Um, Yoon-Jee Kim, Eunwoo Song et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2013 · 103 citations