On chip network: topology design and evaluation using NS2

Abstract

The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the ultra deep submicron technologies that arise from nonscalable global wire delay, failure to archive global synchronization, errors due to signal integrity, nonscalable bus based functional interconnection, etc. In this paper, we introduce interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS2