Embedded high-resolution delay measurement system using time amplification

Abstract

The rapid pace of change in IC technology, specifically in the speed of operation, demands sophisticated design solutions for IC testing methodologies. Moreover, the current technology of System-on-Chip makes great demands on the accurate testing of internal timing parameters as access to internal nodes through input/output pins becomes more difficult. This work presents two high-resolution time measurement schemes for digital Built-in Self-Test (BIST) applications, namely: Two-Delay Interpolation Method and the Time Amplifier. The two schemes are subsequently combined to produce a novel design for BIST time measurement which offers two main advantages: a small time interval measurement capability which advances the state of the art and a small footprint, occupying 0.2 mm2 or equivalent to 3020 transistors, compared with a recent design which has the equivalent of 4800 transistors.