2010 · 12 citations · 8 references
EngineeringVlsi DesignComputer ArchitectureSub-threshold RegimeHardware SecurityInstrumentationParallel Computing4-Bit Asynchronous MultiplierPower-aware DesignAsynchronous CircuitsElectrical EngineeringAsynchronous Completion DetectionComputer EngineeringComputer ScienceSub-threshold Asynchronous MultiplierMicroelectronicsLow-power ElectronicsHardware AccelerationVlsi ArchitectureParallel ProgrammingDigital Circuit Design
A 4-bit Asynchronous multiplier was designed in the sub-threshold regime. The multiplier, using asynchronous completion detection, is more tolerant to process variation than conventional synchronous sub-threshold circuits and operates with a supply voltage as low as 150mV. The average energy per computation was simulated at 1.13pJ. The minimum energy voltage was simulated at 350mV, with an average micro-pipelined frequency of 11.3 kHz.
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Asynchronous Techniques for System-on-Chip Design
Alain J. Martin, M. Nystrom · Proceedings of the IEEE · 2006 · 305 citations
A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency
Bin Zhai, Leyla Nazhandali, Javin Olson et al. · 2006 · 181 citations
Low-power Electronics, Electrical Engineering, Energy Harvesting +15