1998 · 22 citations · 9 references
EngineeringComputer EngineeringComputer ScienceField-programmable Gate ArraysReconfigurable ComputingSystem-on-chip DesignCluster ArchitectureConfigurable Logic BlocksFpga ArchitectureChip PartitioningCluster FormationClusteringHardware PartitioningPartitioningPartitioning AlgorithmsPartitioning StrategiesPerformance-aware Partitioning
This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed methodconsists of three steps: #1# functional-cluster formation, #2# slack computation, and #3# set-coveringbasedpartitioning with functional replication. The proposed methodperforms multi-FPGA partitioning by taking into account path delays and design structural information. We introduce a functional replication technique which performs circuit replications at the functionalcluster level instead of the cell level for delay and interconnect minimization. Experimental results on a number of benchmarks and industrial designs demonstrate that the proposed method achieves high-performance and high-density multi-FPGA partitions. 1 Introduction In general, the traditional HDL-based design #ow from initial speci#cation to multiple-FPGA systems consists of two independent design phases. In the #rst phase, a synthesizer is used to transform an HDL design speci#cation into a CLB-based netlist....
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Circuit partitioning for huge logic emulation systems
Nan-Chi Chou, Lung-Tien Liu, Chung‐Kuan Cheng et al. · 1994 · 61 citations