Design Automation Conference · 1981 · 21 citations · 4 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFormal MethodsHardware Description LanguagesDelay ModelingDigital Logic DesignLogic SynthesisRegister-transfer Level DesignTiming ModelingTiming SemanticsDigital Logic CircuitsHardware SynthesisRegister Transfer Level ImplementationRegister-transfer Level Hardware ModelingRegister-transfer Level SynthesisRegister-transfer Level Timing Analysis
This paper describes a method for formally modelling digital logic using algebraic relations. The types of relations necessary for modelling digital logic at the register-transfer (RT) level are developed. An extension of the model is shown which can be used for logic synthesis at the RT level.1
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Task Allocation in Distributed Data Processing
Chu Chu, Holloway, Min-Tsung Lan et al. · Computer · 1980 · 360 citations