2006 · 26 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingAccelerator ArchitectureConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLow-power Fpga DesignArithmetic Logic Unit ArchitectureArithmetic Unit DesignFixed-point ArithmeticFloating-point ArithmeticFloating-point Unit DesignHigh PerformanceHigh-frequency PerformanceMultiplier Design
Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)
3
Analysis of high-performance floating-point arithmetic on FPGAs
Gokul Govindu, Ling Zhuo, Seonil Choi et al. · 2004 · 138 citations
Rounding algorithms for IEEE multipliers
Mark R Santoro, G. Bewick, Mark Horowitz · 2003 · 79 citations
Engineering, Computer Engineering, Electrical Engineering +11