A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

Abstract

Clocked regenerative comparators, which use positive feedback of a latch to force a fast decision, are used for many applications. In a 10 GHz 3-stage comparator in 1.2 V 0.11 mum CMOS is presented and is designed to extract every 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> bit of a 40 Gb/s data stream. A BER<1012 for 1 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> at the input is achieved. Depending of the intended application, the constant tail current and the low-voltage swing of the CML blocks may or may not be beneficial. In a latch-type sense amplifier (in 1.5V 0.13 mum CMOS) for use in SRAMs is investigated. The delay time is 119 ps for an input voltage difference of 100 mV. A disadvantage is that for proper operation a sufficiently large supply voltage is needed due to the stack of transistors and therefore the comparison time is longer than 11 ns at 0.7 V In a comparator with similar circuit structure in 1.8 V 0.18 mum CMOS is described, consuming 350 muW at 1.4 GHz. The standard deviation of the offset without compensation is delta=31.6 mV. The sense-amplifier presented (1.2V 90nm CMOS, 225 muW @ 2GHz) also consists of a typical latch with two cross-coupled CMOS inverters. The comparator (1.5V 0.12 mum CMOS, low-threshold transistors) reaches a sensitivity (BER=10-9) of 16.5 mV @ 4 GHz/1.5 V and 25.8 mV @ 500 MHz/0.5 V. The design of the latch still needs static current and so 2.65 mW is needed at 6 GHz/1.5 V.