IEEE Design and Test · 2015 · 99 citations · 27 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock Distribution NetworksIntegrated Circuit DesignLow-power Digital Circuit DesignNetwork-on-chip DesignPhysical DesignTiming AnalysisAsynchronous Circuit DesignAsynchronous Digital Circuit DesignAsynchronous ExecutionAsynchronous Sequential CircuitsNetwork-on-chip IntegrationScalabilityScalability Bottlenecks
An asynchronous design paradigm is capable of addressing the impact of increased process variability, power and thermal bottlenecks, high fault rates, aging, and scalability issues prevalent in emerging densely packed integrated circuits. The first part of the two-part article on asynchronous design presents a chronicle of past and recent commercial advances, as well as technical foundations, and highlights the enabling role of asynchronous design in two application areas: GALS systems and networks-on-chip.
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Ivan E. Sutherland · Communications of the ACM · 1989 · 1K citations · Full text
Ivan E. Sutherland, Scott Fairbanks · 2002 · 250 citations
Engineering, Computer Engineering, Electrical Engineering +17