Network-on-chip Integration

Network-On-Chip Integration is a structural design paradigm in Coarse-Grained Reconfigurable Architectures that embeds a packet-switched interconnection network as the primary communication backbone among reconfigurable processing elements, enabling scalable and concurrent data transfer across distributed functional units.

128

Publications

7.2K

Citations

428

Authors

150

Institutions

Publications per year

2017–2026

19

Authors

428

  1. KG
    Kees Goossens

    Eindhoven University of Technology, Netherlands

    6 publications · 1.3K citations

    6

    h-index

  2. FM
    Fernando Moraes

    Pontifícia Universidade Católica do Rio Grande do Sul, Brazil

    6 publications · 168 citations

    6

    h-index

  3. YX
    Yuan Xie

    Pennsylvania State University, United States

    4 publications · 231 citations

    4

    h-index

  4. PV
    Pascal Vivet

    Commissariat à l'Énergie Atomique et aux Énergies Alternatives, France

    4 publications · 260 citations

    4

    h-index

  5. LB
    Luca Benini

    University of Bologna, Italy

    4 publications · 422 citations

    4

    h-index

1–5 of 428

Venues

  1. IEEE Design & Test of Computers

    4 publications · 1.1K citations

    4

    h-index

  2. Journal of Systems Architecture

    JSA · 3 publications · 41 citations

    3

    h-index

  3. Design, Automation, and Test in Europe

    Conference · 3 publications · 295 citations

    3

    h-index

  4. IEEE Communications Magazine

    3 publications · 187 citations

    3

    h-index

  5. IEEE Journal of Solid-State Circuits

    2 publications · 684 citations

    2

    h-index

1–5