28nm advanced CMOS resistive RAM solution as embedded non-volatile memory

Abstract

A back-end integrated Resistive Random Access Memory (ReRAM) (TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti/TiN) in advanced 28nm CMOS process is evaluated. Significant operating margins and high performances identified at device level (read margin, low power set/reset, endurance and retention) are demonstrated to be significantly reduced on larger statistics, i.e. characterized within 1kbit arrays. The High Resistance State (HRS) dispersion, identified as a limiting factor, is modeled through the “tunneling barrier thickness” variation. The optimization through electrical condition tuning is discussed. A global overview of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> material performances is assessed on statistical basis and projection for larger array integration is discussed.