Low dielectric constant materials for microelectronics

TLDR

The drive for higher on‑chip electrical performance has led to copper interconnects, damascene processing, and the development of low‑k dielectrics with added porosity to reduce dielectric constant. This review seeks to classify, characterize, and evaluate low‑k dielectrics, and to identify metrology requirements for pore size, distribution, structure, and mechanical properties. The study focuses on plasma interactions, swelling in liquids, pore sealing, and deposition of thin copper diffusion barriers on porous dielectrics.

Abstract

The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the characteristics and properties of low-k dielectrics. In addition it addresses some of the needs for improved metrology for determining pore sizes, size distributions, structure, and mechanical properties.