International Conference on Computer Aided Design · 1994 · 78 citations · 7 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designSystem-on-chip DesignHardware ArchitectureHigh-level SynthesisLogic SynthesisTiming ModelingVery-large-scale Integration LayoutFloorplanningHardware SynthesisHigh-level Synthesis Timing OptimizationIntegrated Circuit FloorplanningSimultaneous BindingSystem Performance Modeling
As device feature size decreases, interconnection delay becomes the dominating factor of system performance. Thus it is important that accurate physical information is used during high level synthesis. In this paper, we consider the problem of simultaneously performing functional-unit binding and floorplanning. Experimental results indicate that our approach to combine binding and floorplanning is superior to the traditional approach of separating the two tasks.
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A New Algorithm for Floorplan Design
Martin D. F. Wong, C. L. Liu · Design Automation Conference · 1986 · 478 citations
Architecture, Industrial Engineering, Algorithmic Design +12
Jen-Pin Weng, Alice C. Parker · 1991 · 107 citations