Computational aspects of optical lithography extension by directed self-assembly

TLDR

EUV insertion timing for high‑volume manufacturing remains uncertain due to source power and mask infrastructure limits, while directed self‑assembly offers a cost‑effective alternative to extend optical lithography to the 10 nm node and beyond. The paper investigates the technical prospects of DSA technology in computational design‑for‑manufacturing, aiming to identify design restrictions and develop a full‑chip computational patterning solution. The authors built an in‑house prototype computational patterning toolset for early design‑technology co‑optimization, described the DSA computational lithography infrastructure with via and fin examples, and outlined ecosystem requirements and EDA vendor roles to make DSA lithography a full‑chip viable technology. Early wafer data from a DSA test mask built with the new toolsets confirm initial feasibility of the approach.

Abstract

EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.