2007 · 11 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSystem-on-chip DesignClock Distribution NetworksClock ManagementCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignClock Buffer DesignClock DistributionClock Distribution DesignClock JitterFrequency TuningJitterJitter CompensationJitter Mitigation
A low-jitter LC-based clock distribution in 0.13μm CMOS uses a frequency-tuning technique based on a voltage-swing digitizer. Optimum jitter performance is achieved by adaptively adjusting the injection-lock ratio. The efficiency of this technique results in 25% power-savings in the clock buffer for similar or better jitter performance.
8
A 4.6GHz resonant global clock distribution network
S.C. Chan, P.J. Restle, Kenneth L. Shepard et al. · 2004 · 84 citations
Engineering, Computer Engineering, Electrical Engineering +17
10GHz clock distribution using coupled standing-wave oscillators
Frank O’Mahony, C. Patrick Yue, Mark Horowitz et al. · 2003 · 35 citations