Bryan Casper - Concepedia

Author

Bryan Casper

Intel (United States)

Also Known As

B. Casper, B.K. Casper, BRYAN K. CASPER, Bryan Casper, Bryan K. Casper

Publications

2.4K

Citations

H-Index

Concepts

All Affiliations

Intel (United States)University of British Columbia

About

Bryan Casper is an author at Intel (United States) specializing in engineering, computer engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	29	48	2.2K
2	Computer Engineering	26	40	1.9K
3	Computer Science	3	3	436
4	Education	2	2	39
5	Applied Physics	2	2	108

Bryan Casper

Publications

2.3K

Citations

H-Index

Page 1

	Year	Citations
An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes Bryan Casper, M. Haycock, Randy Mooney Hardware SecuritySystem On ChipEngineeringVlsi DesignMixed-signal Integrated Circuit	2003	238
A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS Ganesh Balamurugan, Joseph Kennedy, Gaurab Banerjee, IEEE Journal of Solid-State Circuits Low-power ElectronicsPassive EqualizationElectrical EngineeringEngineeringVlsi Design	2008	143
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial Bryan Casper, Frank O’Mahony IEEE Transactions on Circuits and Systems I Regular Papers EngineeringClocking InfrastructureComputer ArchitectureSystem-level DesignMeasurement Techniques	2009	114
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control Hao Li, Ganesh Balamurugan, Taehwan Kim, IEEE Journal of Solid-State Circuits EngineeringOptical Transmission SystemOptical ModulationNonlinear EqualizationIntegrated Circuits	2020	101
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew James Jaussi, Ganesh Balamurugan, David R Johnson, IEEE Journal of Solid-State Circuits Adaptive Receiver-side EqualizationEngineeringClock RecoveryData ConverterMixed-signal Integrated Circuit	2005	100
An 8-Gb/s simultaneous bidirectional link with on-die waveform capture Bryan Casper, A. Martin, James Jaussi, IEEE Journal of Solid-State Circuits PhotonicsOn-die Waveform CaptureEngineeringClock RecoveryData Converter	2003	96
Modeling and Analysis of High-Speed I/O Links Ganesh Balamurugan, Bryan Casper, James Jaussi, IEEE Transactions on Advanced Packaging EngineeringVlsi DesignTransmit JitterComputer ArchitectureTransmission System	2009	84
A 112 Gb/s PAM4 Silicon Photonics Transmitter With Microring Modulator and CMOS Driver Hao Li, Bryan Casper, Ganesh Balamurugan, Journal of Lightwave Technology Photonic DevicePhotonicsGb/s Pam4 TransmitterEngineeringOptical Transmission System	2019	73
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS Hao Li, Ganesh Balamurugan, James Jaussi, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignGb/s Pam4 Data	2018	65
A 47$\,\times\,$10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS Frank O’Mahony, James Jaussi, Joseph Kennedy, IEEE Journal of Solid-State Circuits Gb/s 1.4EngineeringVlsi DesignClock SignalsNm Cmos	2010	62

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