High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder

Abstract

In carry-select adders (CSAs), using a single ripple carry adder and a first zero finder (FZF) circuit instead of dual ripple carry adder has an impressive impact on reduction of number of transistors and so power consumption of adder. On the other hand, combination of CSA and carry-lookahead adder (CLA) improves speed of this adder. In this paper a 64-bit static adder with structure of a hybrid CLA/CSA is presented. This adder operates with low power and occupies lower area in comparison to conventional CSA circuit due to using a first zero finder circuit. Besides by three basic changes in the critical path of adder, speed is improved considerably; First of all we used a high speed compact CLA as partial adder in each block, then a block carry generator (BCG) circuit is used for faster carry propagation and finally we replaced multiplexer gate with a XNOR gate. This circuit is implemented in TSMC 0.18μm CMOS technology at 1.8V power supply. Critical path delay of this adder decreased to 592ps, equivalent to 7.6 FO4 (fanout-of-4) inverter delays.