Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions

Abstract

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving both increased functional convergence as well as increased packaging complexity and sophistication. This is driving an unprecedented demand to increase the variety of wafer level, thin POP (Package on Package), and TSV (Through Silicon Via)/Interposer packaging solutions. It is expected to see more exciting interconnect technologies of wafer level packaging such as TSV, 2.5D Interposers, eWLB (embedded Wafer Level Ball Grid Array)/FO-WLP (Fan Out Wafer Level Package) to meet these needs. FO-WLP/eWLB has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. eWLB technologies are leading the way to the next level of thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple-die in very reliable, low-profile/low-warpage 2.5D and 3D solutions. The use of these embedded FO-WLP packages in a side-by-side configuration to replace a stacked package configuration, and to utilize as the base for a 3D TSV configuration, is critical to enable a more cost effective mobile market capability. Combining the analog and memory device with digital device packaging capability can provide an optimum solution for achieving the best performance in thin multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards packaging technologies with extended-die/fanout flipchip technology. Package and substrate design study, mechanical and thermal characterization of flipchip eWLB solution over high-end flipchip would be presented.