Concepedia

A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

Kang-Wei Hsueh, Yu-Kai Chou, Yu-Hsuan Tu, Yi-Fu Chen, Ya-Lun Yang, Hung-Sung Li

2008 · 34 citations · 6 references

Concepts

EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersBackground CalibrationCmos Analog Integrated CircuitsCmos Digital Circuit DesignPipelined Digital Circuits

Abstract

This paper demonstrates a IV 200MS/s pipelined ADC with digital background calibration in 65nm digital CMOS process.

References

6

Background calibration techniques for multistage pipelined ADCs with digital redundancy

Jipeng Li, Un-Ku Moon · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2003 · 232 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter

K. Nair, R. Harjani · 2004 · 43 citations

Engineering, Computer Engineering, Electrical Engineering +17

A split-ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC

John McNeill, Michael C. W. Coln, B.J. Larivee · 2005 · 43 citations

Engineering, Electrical Engineering, Analog Electronics +15

A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC

E. Siragusa, Ian Galton · 2004 · 42 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 15b 20MS/s CMOS pipelined ADC with digital background calibration

Hung Chih Liu, Zwei Mei Lee, Jieh-Tsorng Wu · International Solid-State Circuits Conference · 2004 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +12