Background calibration techniques for multistage pipelined ADCs with digital redundancy

TLDR

The paper proposes a digital background calibration scheme for multistage ADCs that corrects linearity errors from capacitor mismatches and opamp gain, and introduces a two‑channel architecture to enhance digital‑correlation efficiency. The method recalculates outputs using each stage’s equivalent radix, extracted via background digital correlation, leveraging the digital redundancy of pipelined ADCs and a two‑channel architecture for efficient calibration. Simulations show that the calibration preserves SNR and achieves 16‑bit linearity despite 0.1 % capacitor mismatches and 60 dB opamp gain.

Abstract

The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage's equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with /spl sigma/=0.1% capacitor mismatches and 60 dB opamp gain.