A split-ADC architecture for deterministic digital background calibration of a 16b 1MS/s ADC

Abstract

Self-calibration in fewer than 10,000 conversions is demonstrated in a 16b, 1 MS/s algorithmic ADC. A split-ADC architecture enables continuous digital background calibration. The analog sub-system of the ADC is implemented in 0.25 /spl mu/m CMOS, consumes 105 mW and has a die size of 1.2/spl times/1.4 mm/sup 2/.