Design of Control unit for Low Power AU Using Reversible Logic

Abstract

Abstract Reversible Logic is becoming one of the potentialpower optimization techniquesin Low Power CMOS design,and also finds its application in Quantum Computing and Nanotechnology. With the advancement in VLSI design technology which offers exponentially shrinking of device dimensions and exponentially growing circuit complexities, device scaling is critically limited by the power dissipation; demanding for better power optimizations methods like Reversible Logic. The basic building block any computational unit is arithmetic unit. Hence in this paper Reversible Arithmetic which offers a high power optimization is built by using suitable control logic to one of the input variables of parallel adder anddifferent basic arithmetic operations areimplemented. In our design, the full Adders are realized using synthesizable, low quantum cost, low garbage output Peres gates andoperations such as data transfer, addition, subtraction, increment, decrementetc are realized using reversible gates.