IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1986 · 92 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign AutomationDesign OptimizationCombinational Logic DescriptionDesign SynthesisHigh-level SynthesisLogic SynthesisTiming AnalysisTiming ModelingArea-delay TradeoffsCombinational Logic DesignCombinational Logic SynthesisFunctional CorrectnessMulti-level Logic DesignStandard Cell SynthesisTimingTiming Constraints
The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a synthesis system capable of generating combinational logic in a given technology under user-defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. Applied to a large number of examples, the system has successfully traded off area versus delay and performs optimized, delay-constrained, multilevel synthesis into standard cell libraries.
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LSS: A system for production logic synthesis
John A. Darringer, Daniël Brand, John V. Gerbi et al. · IBM Journal of Research and Development · 2000 · 140 citations
LSS: A system for production logic synthesis
John A. Darringer, Daniël Brand, John V. Gerbi et al. · IBM Journal of Research and Development · 1984 · 136 citations