Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs

Abstract

A convenient optimization method using a circuit simulator SPICE2 with realistic models for short-channel MOSFETs and capacitances is described. By using this method, MOSFET size optimization is carried out and it is found that the optimum size ratio of NMOS versus PMOS shifts from the simple theory of S. Flannagan (ibid., vol 20, p.880-2, 1985). NMOS size should be larger than PMOS size. This is due to the velocity saturation carriers in short-channel MOSFETs. The effects of the parasitic PMOS and NMOS sizes, supply voltage, and temperature are also considered. It is also shown that the symmetry of the cross-coupled NANDs and insertion of cascaded inverters do not help the optimization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>