Controllable Inverter Delay and Suppressing V<inf>th</inf> Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture

Abstract

45 nm-gate SOTB (silicon on thin BOX) technology for LSTP application has been successfully developed. In the SOTB device, short-channel effect immunity without channel doping and back-gate bias threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) control are demonstrated. GIDL is reduced with avoiding drive current and inverter delay degradation minimum by optimizing offset source/drain extension to gate overlap. We have also proposed the SOTB device design enabling the controllable inverter delay and low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> fluctuation for logic and SRAM memory cell transistors. Inverter delay can be improved from 19.3 to 10.5 ps by applying the forward back-gate bias. Furthermore, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> fluctuation can be reduced about 16% by applying the reverse back-gate bias. A 6-transistor SRAM memory cell of the SOTB structure by adding a reverse back bias control has shown to dramatically improve SRAM memory cell stability.