1996 · 55 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringDesign AutomationField-programmable Gate ArraysMicroelectronicsDesign For TestabilityDigital Integrated Circuit DesignField-programmable Gate Array ArchitectureHardware Modeling For Digital SystemsLogic SynthesisParameterized DesignDigital Logic CircuitsGate Array DesignGraph-theoretic Layout AnalysisHardware GenerationNetlist GenerationParameterized Hardware GenerationPlacement
The development of new Field-Programmed, Mask-Programmed and Laser-Programmed Gate Array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic random circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the random circuit generation. To validate the quality of the generated netlists, parameters that are not specied in the generation are c ompared with those of real circuits, and with those of \random" graphs. rameter which i s a c haracteristic of the circuit in question.
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A technique for drawing directed graphs
Emden R. Gansner, E. Koutsofios, Stephen C. North et al. · IEEE Transactions on Software Engineering · 1993 · 675 citations