Gate-First Processed FUSI/HfO<inf>2</inf>/HfSiO<inf>x</inf>/Si MOSFETs with EOT=0.5 nm - Interfacial Layer Formation by Cycle-by-Cycle Deposition and Annealing

Abstract

We have successfully fabricated a 0.5 nm FUSI-NiSi/ HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> / Si gate stack structure with the gate-first process. The HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> interfacial layer was formed by the cycle-by-cycle deposition and annealing process, followed by the in-situ layer-by-layer deposition and annealing for HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> growth. The gate leakage current of ~ 10 A/cm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fb</sub> - 1.0 V and the effective electron mobilityof 120 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs at 0.8 MV/cm were obtained for n-MOSFET with EOT = 0.49 nm.