2012 · 22 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDynamic Power ReductionLow-power Digital Circuit DesignTiming AnalysisVoltage ScalingCmos ScalingLow-voltage Cmos DesignMemory Circuit DesignOperating VoltagePerformance DegradationUltra-low-power CmosVoltage
A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V.
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