IEEE Journal of Solid-State Circuits · 1986 · 19 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyLeakage Power ReductionMemory DevicesMemory Subsystem DesignCmos Analog Integrated CircuitsImpurity ControlLow-voltage Cmos DesignMemory Circuit DesignNon-volatile Cmos MemorySense Amplifier Design
A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.
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A 20ns static column 1Mb DRAM in CMOS technology
K. Satō, H. Kawamoto, Kazumasa Yanagisawa et al. · 1985 · 27 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 1Mb CMOS DRAM with fast page and static column modes
S. Saito, Shosuke Fujii, Yoichi Okada et al. · 1985 · 18 citations
Engineering, Computer Engineering, Electrical Engineering +13