Modeling the inter-electrode capacitances of Si CoolMOS transistors for circuit simulation of high efficiency power systems

Abstract

The CoolMOS™ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> transistor is a power MOSFET type device that utilizes a “super-junction” embedded within its drift region in order to improve the trade-off between on-resistance and breakdown voltage. The super-junction results in unique inter-electrode capacitance characteristics that require an advanced modeling approach to accurately represent switching performance. This paper describes a new compact circuit simulator model for the CoolMOS™ transistor and demonstrates the model performance using the Saber <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">†</sup> simulator for a 650 V, 60 A device. The model is suitable for implementation in the Saber simulator that accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. Simulation results show excellent agreement with measurement results in contrast to previous modeling approaches used for this device. The compact model developed in this work is going to be utilized in the design of a high efficiency soft-switching inverter for electric vehicle motor drives and a high efficiency bidirectional DC-DC converter at zero-voltage switching (ZVS) operation.