IEEE Design & Test of Computers · 2010 · 148 citations · 15 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSystem-on-chip DesignInterconnect ArchitectureLatency OptimizationNetwork Performance AnalysisNetwork-on-chip DesignPerformance OptimizationTask SchedulingDynamic Task SchedulingHeuristicsNetwork Latency OptimizationNetwork-on-chipNetwork-on-chip ArchitecturesOn-chip NetworksSystem Design OptimizationTask Mapping
Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.
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