Energy- and performance-aware mapping for regular NoC architectures

TLDR

The paper proposes an algorithm that maps IP blocks onto a regular NoC to minimize communication energy while meeting specified performance constraints. The authors formulate the energy‑ and performance‑aware mapping problem, exploit routing flexibility to enlarge the solution space, and solve it with an efficient branch‑and‑bound algorithm that ensures deadlock‑free deterministic routing. Experiments demonstrate the algorithm runs quickly and yields substantial energy savings, achieving an average 51.7 % reduction for a complex video/audio application compared to an ad hoc implementation.

Abstract

In this paper, we present an algorithm which automatically maps a given set of intellectual property onto a generic regular network-on-chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. At the same time, the performance of the resulting communication system is guaranteed to satisfy the specified design constraints through bandwidth reservation. As the main theoretical contribution, we first formulate the problem of energy- and performance-aware mapping in a topological sense, and show how the routing flexibility can be exploited to expand the solution space and improve the solution quality. An efficient branch-and-bound algorithm is then proposed to solve this problem. Experimental results show that the proposed algorithm is very fast, and significant communication energy savings can be achieved. For instance, for a complex video/audio application, 51.7% communication energy savings have been observed, on average, compared to an ad hoc implementation.