Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Abstract

We present circuit design aspects of fully depleted extremely thin SOI (ETSOI) enabling 22 nm low-power CMOS and beyond, and demonstrate that all devices including analog, I/O, and passive devices can be fabricated in the thin silicon layer. Excellent device matching, g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> scaling to small gate length, good RF performance, and absence of history effect are the main features of the ETSOI technology.