1980 · 19 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryComputer-aided DesignDesign AutomationDesign HierarchyIntegrated Circuit DesignLayout DesignLayout EvaluationPhysical DesignVery-large-scale Integration LayoutCircuit TopologyComputer-aided Design For Integrated CircuitsIc Physical Design VerificationLayout TechniquesLayout VerificationLayout Versus Schematic CheckingLayout Versus Schematic VerificationVerification Of Integrated Circuits
This paper describes a CAD program which checks the circuit topology and the electrical parameters from the IC layout data against the user supplied circuit descriptions. Taking advantage of the hierarchical characteristics of the layout data, the program achieves an efficient analysis and does a clear presentation of the results.
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An artwork design verification system
Henry S. Baird, Y. E. Cho · Design Automation Conference · 1975 · 38 citations