Concepedia

Layout Versus Schematic Checking

Layout Versus Schematic Checking is a verification methodology in Very-Large-Scale Integration design that ensures the geometric representation of a circuit layout accurately corresponds to its intended schematic diagram by systematically comparing connectivity, device identities, and topological relationships.

18

Publications

402

Citations

54

Authors

23

Institutions

Publications per year

2017–2026

3

Variants

LvsLvs Checking

Parents

Publications

18

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

Coenrad J. Fourie · IEEE Transactions on Applied Superconductivity · 2014 · 54 citations

, , +16

An artwork design verification system

Henry S. Baird, Y. E. Cho · Design Automation Conference · 1975 · 38 citations

, , +15

A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers

Carsten Wulff, Trond Ytterdal · IEEE Journal of Solid-State Circuits · 2017 · 37 citations

, , +17

ESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism

R. Zhan, Haigang Feng, Q. Wu et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 30 citations

, , +14

A Cadence-based design environment for single flux quantum circuits

V. Adler, Chin-Hong Cheah, Kris Gaj et al. · IEEE Transactions on Applied Superconductivity · 1997 · 26 citations

, , +17

1–5 of 18

Authors

54

  1. CJ
    Coenrad J. Fourie

    Stellenbosch University, South Africa

    2 publications · 65 citations

    2

    h-index

  2. AL
    André Leblond

    Teem Photonics (France), France

    1 publications · 11 citations

    1

    h-index

  3. TS
    Theo Smedes

    NXP (Netherlands), Netherlands

    1 publications · 22 citations

    1

    h-index

  4. SC
    Shiu-Ping Chao

    Texas Instruments (United States), United States

    1 publications · 19 citations

    1

    h-index

  5. KM
    Katsuyuki Machida

    NTT (Japan), Japan

    1 publications · 23 citations

    1

    h-index

1–5 of 54

Institutions

23

  1. NTT (Japan)

    Tokyo, Japan

    2 h-index

    5 publications

    94 citations

  2. IBM (United States)

    Armonk, United States

    2 h-index

    2 publications

    37 citations

  3. Stellenbosch University

    Stellenbosch, South Africa

    2 h-index

    3 publications

    76 citations

  4. University of Rochester

    Rochester, United States

    1 h-index

    5 publications

    130 citations

  5. Voronezh State University of Forestry and Technologies

    Voronezh, Russia

    1 h-index

    2 publications

    44 citations

  6. Tokyo Institute of Technology

    Tokyo, Japan

    1 h-index

    1 publications

    23 citations

  7. Yale University

    New Haven, United States

    1 h-index

    1 publications

    11 citations

  8. Taiwan Semiconductor Manufacturing Company (United States)

    San Jose, United States

    1 h-index

    1 publications

    26 citations

1–8 of 23

Venues

  1. Design Automation Conference

    Conference · 4 publications · 71 citations

    4

    h-index

  2. 3

    h-index

  3. 2

    h-index

  4. IEEE Journal of Solid-State Circuits

    1 publications · 37 citations

    1

    h-index

  5. Modeling of systems and processes

    1 publications · 22 citations

    1

    h-index

1–5