Concepedia

Layout Versus Schematic Verification

Layout Versus Schematic Verification is a formal design validation method in integrated circuit development that systematically checks for structural and connectivity equivalence between the physical layout and its corresponding circuit schematic to ensure fabrication accuracy.

34

Publications

742

Citations

118

Authors

48

Institutions

Publications per year

2017–2026

4

Variants

Layout Versus SchematicLvs

Parents

Publications

34

Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

Sandeep Kumar Samal, Deepak Kumar Nayak, Motoi Ichihashi et al. · 2016 · 73 citations

, , +17

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

Coenrad J. Fourie · IEEE Transactions on Applied Superconductivity · 2014 · 54 citations

, , +16

An artwork design verification system

Henry S. Baird, Y. E. Cho · Design Automation Conference · 1975 · 38 citations

, , +15

Whole-chip ESD protection design verification by CAD

Lin Lin, Xin Wang, He Tang et al. · 2009 · 34 citations

, , +13

Experimental and computational contribution to chip geometry evaluation when micromilling Inconel 718

Déborah de Oliveira, Milla Caroline Gomes, Gustavo Vilela Oliveira et al. · Wear · 2021 · 33 citations

, , +15

1–5 of 34

Authors

118

  1. EB
    Erich Barke

    Leibniz University Hannover, Germany

    3 publications · 63 citations

    3

    h-index

  2. TH
    T. Hoepken

    Leibniz University Hannover, Germany

    2 publications · 37 citations

    2

    h-index

  3. FL
    F. Luellau

    Leibniz University Hannover, Germany

    2 publications · 37 citations

    2

    h-index

  4. CJ
    Coenrad J. Fourie

    Stellenbosch University, South Africa

    2 publications · 65 citations

    2

    h-index

  5. ZL
    Ziyang Lu

    Siemens (Hungary), Hungary

    2 publications · 27 citations

    2

    h-index

1–5 of 118

Institutions

48

  1. Siemens (Hungary)

    Budapest, Hungary

    3 h-index

    8 publications

    123 citations

  2. Intel (United States)

    Santa Clara, United States

    3 h-index

    3 publications

    55 citations

  3. Leibniz University Hannover

    Hanover, Germany

    3 h-index

    7 publications

    137 citations

  4. Mentor Technologies

    Tulsa, United States

    2 h-index

    3 publications

    54 citations

  5. Stellenbosch University

    Stellenbosch, South Africa

    2 h-index

    3 publications

    76 citations

  6. Industrial Technology Research Institute

    Hsinchu, Taiwan

    1 h-index

    2 publications

    20 citations

  7. Technical University of Munich

    Munich, Germany

    1 h-index

    1 publications

    14 citations

  8. Voronezh State University of Forestry and Technologies

    Voronezh, Russia

    1 h-index

    2 publications

    44 citations

1–8 of 48

Venues

  1. Design Automation Conference

    Conference · 4 publications · 92 citations

    4

    h-index

  2. 3

    h-index

  3. IEEE Design & Test of Computers

    3 publications · 36 citations

    3

    h-index

  4. 21st Design Automation Conference Proceedings

    Conference · 2 publications · 37 citations

    2

    h-index

  5. 2

    h-index

1–5