Statistics
Publications
3
Citations
39
H-Index
3
Active since
2010
Affiliations
Siemens (Hungary)(Current)
Ziyang Lu is an author at Siemens (Hungary) specializing in computer engineering, verification, and formal verification.
Publications per year
2010–2012
3
3
A framework for logic-aware layout analysis
P. J. Gibson, Ziyang Lu, Fedor G. Pikus et al. · 2010 · 16 citations
Engineering, Hardware Verification Language, Electronic Design Automation +20
Static low power verification at transistor level for SoC design
J. Lescot, Vincent Bligny, Dina Medhat et al. · 2012 · 12 citations
Transistor-level Verification Flow, Transistor Level, Vlsi Design +21
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