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Non-destructive defect depth determination at fully packaged and stacked die devices using Lock-in Thermography
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2010
Year
Unknown Venue
EngineeringMeasurementEducationSingle ChipAdvanced Packaging (Semiconductors)CalibrationInstrumentationElectronic Packaging3D Ic ArchitectureHardware ReliabilityNondestructive TestingChip On BoardStructural Health MonitoringComputer EngineeringChip AttachmentDevice ReliabilityMicroelectronicsPhysic Of FailureDefect LocalizationChip-scale PackageApplied PhysicsDie DevicesLock-in ThermographyThermal Wave Propagation
This paper will present a new non-destructive approach for the 3D localization of thermally active buried defects in single chip and stacked die architectures by use of Lock-in Thermography (LIT). The basic principles concerning the thermal wave propagation through different material layers and the resulting phase shift will be presented and discussed. Based on that, the LIT application for 3D defect localization will be evaluated at both fully packaged single chip and stacked die devices by comparing theoretical and experimental data.
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