Threshold voltage margin of normally-off GaAs MESFET in DCFL circuit

Abstract

The margin of threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ) for GaAs normally-off MESFET DCFL's was numerically analyzed applying the equivalent inverter circuit model. The results show that the optimum (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ) is 0.3 V. Quantitative relation between the margin and delay time is obtained as a function of (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ). At (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ) = 0.3 V, the margin is 0.28 V with t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</inf> less than 100 ps for 0.5 µm gate length.