Charge trapping in very thin high-permittivity gate dielectric layers

Abstract

The trapping of charge carriers in very thin SiOx/ZrO2 and SiOx/TiO2 gate dielectric stacks during constant gate voltage stress of metal–oxide–semiconductor capacitors has been investigated. The increase of the gate current density observed during the gate voltage stress has been analyzed, taking into account both the buildup of charges in the layer as well as the stress-induced leakage current contribution. From data analysis, the cross section of traps generated during the electrical stress is estimated. It is suggested that these traps are probably ZrOH and TiOH neutral centers that are related to the breaking of bridging O bonds by mobile H+ protons followed by the trapping of these protons at ZrO or TiO sites.