High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process

Abstract

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 μm EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting high pixel yield, high quantum efficiency and low dark current are demonstrated.